1. Field of the Invention
The present invention relates to a system for checking the clock synchronization control in the demodulating section of a digital communication equipment.
2. Description of the Related Art
In a digital mobile communication equipment, control for proper clock synchronization between a transmitting signal and a received signal in its demodulating section is an important technological issue.
Whether a signal demodulating circuit properly performs clock synchronization control in accordance with a phase error generated in a received baseband signal so as to receive an error-free digital signal is an important check item in developing new signal demodulating circuits and an important test item in mass-producing such circuits.
In order to check for proper clock synchronization control in the demodulating section, it is necessary to conduct a test while changing the phase of the received signal. There was a test in which digital data modulated at a digital modulator is directly inputted to a demodulator. However, this test cannot check whether the clock synchronization control is properly performed in the demodulator because the phase of the received signal is not changed.
According to a conventional clock synchronization control check system, in the event that a phase error is generated, the clock synchronization is checked in such a manner that modulated digital data generated at the digital modulator is converted into an analog signal through a digital-to-analog (D/A) converter which in turn is converted into a digital signal through an analog-to-digital (A/D) converter while providing phase errors by changing the sampling clock of the A/D converter.
Referring to FIG. 9, which shows such conventional clock synchronization control check system, reference numeral 100 represents a part of a demodulation circuit to be checked, and reference numeral 200 represents the clock synchronization control check system. The elements 100 and 200 constitute a modem in a conventional baseband signal transmitter/receiver modem of a differential-phase-shift keying (DPSK) type in which section (a) is a modulating section and section (b) is a demodulating section.
In DPSK, the sign of a digital baseband signal corresponds to a phase shift between two consecutive symbols. In the modulating section (a), a digital input signal supplied from a data generator 120 is subjected to orthogonal separation at an in-phase component/orthogonal component (I/Q) separator 101, which in turn is subjected to modulation at a differential-phase-shift-keying modulator 102, and then subjected to filtering at root cosine roll-off (RCROF) filters 103-1 and 103-2 for the I and Q components to suppress inter-symbol interference so as to produce a modulated digital data. The modulated digital data is then converted into analog signals at D/A converters 109-1 and 109-2.
In the demodulating section (b), the analog signals are converted into digital signals at A/D converters 110-1 and 110-2, which are demodulated through RCROF filters 104-1 and 104-2, a demodulator 105, a detector 106, and an I/Q synthesizer 107. A received-clock reproduction circuit 108 extracts clock components from outputs of the demodulator 105 and reproduces a clock signal. The reproduced clock signal is supplied to the A/D converters 110-1 and 110-2 as a clock for the A/D converter.
In the clock synchronization control test, the phase of the clock is adjusted by delaying or advancing the clock signal through a phase delay circuit 111, and the error rate is measured by an error rate meter (not shown). Whether or not the clock phase is properly adjusted is judged based on the error rate.
As described above, in the conventional system, the clock synchronization control is checked on a hardware basis. Accordingly, when it is judged that clock synchronization control is not properly performed, it is difficult to locate a faulty part in the clock reproduction circuit. Further, the hardware must actually be constructed to change the clock phase, and it is difficult to provide any desired phase error to the clock on the hardware basis. Accordingly, the conventional system requires a great amount of time and cost for the clock synchronization control check.